GaAs Via Hole
SEM View into a GaAs Via Hole
Test Via
SEM of a Test Via after Dry Etching and Electroplating

Backside Process of RF Devices

The back side process creates the desired functionality of the back side of the wafer. After protecting the front side of the wafer with a protective coating the wafer is bonded front side down on a carrier. After thinning the wafer to a thickness down to 100 µm, metal layers for the bonding process and for thermal contacting are deposited.

For applications in the micro wave range short wires are often desirable, as they can enhance the high frequency properties. This aim is achieved by means of through wafer vias that connect front side and back side electrically. These vias can be formed either by laser drilling or by plasma etching. After deposition of a conducting starting layer the vias are filled by means of galvanic metal deposition.

Standard method

  • Back-side processing up to 4" (GaAs) and 3" (SiC/GaN) wafers respectively
  • Typical diameter of a via of 60 µm
  • Via machining using plasma etching and / or laser ablation

Contact

Dr. Andreas Thies
 Phone +49.30.6392-3297
 Fax +49.30.6392-2685
 Email andreas.thies(at)fbh-berlin.de